VLSI circuit defect diagnosis: open defects and run-time speed

To shorten time-to-market of VLSI circuit chips, the yield must be ramped up by quickly discovering and rectifying the causes for systematic defects. Due to the shrinking feature size of devices 90nm and below, yield ramp up is becoming more and more difficult. Volume diagnosis with statistical learning is needed to cost effectively discover systematic defects. An accurate and high throughput diagnosis tool is required to diagnose large numbers of failing devices to aid statistical yield learning. In this work, we propose techniques to improve diagnosis accuracy and resolution, techniques to improve run-time performance. We consider the problem of determining the location of open defects in interconnects of deep submicron designs. We investigate a procedure that uses minimal information beyond the circuit net lists and give experimental results to demonstrate the defect resolution obtained using the method. The additional information used by the proposed method is a list of nodes in the neighborhoods of circuit nodes and the circuit layout. Specifically, difficult to determine circuit parameters of manufactured instances of a design such as coupling capacitances between circuit nodes and threshold voltages of gates in the circuit are not needed to use the proposed diagnosis procedure. A dictionary called NFB dictionary of small size and does not grow linearly with pattern count is proposed. It further reduced dictionary size over previous dictionary while still achieve higher failing pattern diagnosis performance than industry standard Effect-Cause diagnosis procedures. In this work we also propose a method to achieve higher speedup with a marginally larger dictionary than the NFB dictionary. We achieve this by identifying a set of faults called hyperactive faults for which we create a novel dictionary. Hyperactive faults tend to propagate fault effects to many observation points and cost a large amount of time to simulate.